Chapter 7. Testing & Integration

Because MIL-STD-1553 is used in mission-critical and safety-critical systems, verifying compliance is not optional—it is mandatory. Testing ensures that a device not only communicates correctly but also does not disrupt the bus if it fails. 

7.1 The SAE Test Plans

The Society of Automotive Engineers (SAE) has established the standard "test plans" that all 1553 equipment must pass. These are the bible for verification.

• SAE AS4111 (RT Validation Plan): The rigorous "design qualification" test. It involves thousands of test cases, injecting errors (like bad parity, wrong Manchester timing, and zero-crossing errors) to ensure the RT detects them and rejects the message without crashing.
• SAE AS4112 (RT Production Plan): A subset of the validation plan used for every unit coming off the assembly line.
• SAE AS4113/4114: The equivalent test plans for Bus Controllers.
• SAE AS4115: Test Plan for the Digital Time Division Command/Response Multiplex Data Bus System.
• SAE AS4116: Test Plan for the Digital Time Division Command/Response Multiplex Data Bus Bus Monitors.
• SAE AS4117: Test Plan for the Digital Time Division Command/Response Multiplex Data Bus Couplers, Terminators, and Data Bus Cables.

7.2 Common Error Types

A robust 1553 interface must handle "dirty" bus conditions gracefully.

7.2.1 Electrical Errors

• Zero Crossing Deviation: If the signal transition does not occur exactly at the mid-bit point (within ±150ns), the receiver must reject the word.
• Amplitude Violations: Signals that are too low (weak driver) or too high (clipping) must be handled according to the threshold specs.

7.2.2 Protocol Errors

• Parity Error: If the parity bit does not result in Odd Parity, the word is invalid.
• Word Count Error: If a message contains fewer or more words than the Command Word specified, the RT must reject the entire message.
• Contiguity Error: If there is a gap (typically >2 µs) between data words, the message is declared invalid.

 7.3 The Holt Advantage: Built-In Bus Monitor (MT)

Traditionally, debugging a 1553 bus required expensive external Bus Analyzers. However, Holt’s HI-6130 and HI-6131 offer a powerful alternative: they can function as a Monitor Terminal (MT).

7.3.1 System Debugging

Designers can configure a Holt device in "SMT" (Simple Monitor Terminal) mode on their development board.

• Function: In this mode, the chip "snoops" all traffic on the bus without transmitting.
• Benefit: It captures every command, status, and data word into a circular buffer in RAM. The host processor can read this buffer to log traffic, verify message sequencing, and diagnose software issues without needing external equipment.

7.3.2 Flight Test Recorders (IRIG-106)

For flight test instrumentation, the HI-6130 and HI-6131 support IMT (IRIG-106 Monitor Terminal) mode.

• Packetizing: The chip automatically groups 1553 messages into packets with a 48-bit timestamp and a Block Status Word, formatted specifically for the IRIG-106 Chapter 10 standard.
• Holt Exclusive: This hardware offload allows a simple flight recorder to capture high-fidelity bus data with almost zero CPU overhead, a feature unique to Holt's architecture.

Appendix A.