The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains a Bus Controller (BC), a Bus Monitor Terminal (MT) and two independent Remote Terminals (RTs). Any combination of the contained 1553 functions can be enabled for concurrent operation. The enabled terminals communicate with the MIL-STD-1553 buses through a shared on-chip dual bus transceiver and external transformer. The user allocates 64K bytes of on-chip static RAM between devices to suit application requirements.
Two options are offered for host access to internal registers and static RAM:
- The HI-6130 uses a 16-bit parallel bus
- The HI-6131 communicates with the host via a 4-wire serial peripheral interface (SPI).
Package options vary, based on host interface I/O pin count.
Programmable interrupts provide terminal status to the host processor. Circular data stacks in RAM have rollover and programmable “level attained” interrupts. The HI- 613x can be configured for automatic self-initialization after reset. A dedicated SPI port reads data from an external serial EEPROM to fully configure registers and RAM for any subset of one to four terminal devices.
Software
Various software support options are available for the HI-6131. A development kit (ADK-6131) includes low level software that demonstrates the broad features of the device. The API Application Development Kit (ADK-6131API) includes Holt's MIL-STD-1553 Application Programming Interface (API) library. In addition, Linux and Bare Metal (ARM) Software Drivers are available. Details are outlined below.
Features
- MIL-STD-1553B/C, MIL-STD-1760, SAE AS15531A and STANAG 3838 compliant
- Concurrent multi-terminal operation for one to four MIL-STD-1553B functions: BC, MT and two independent RTs.
- Third Party RT Validated.
- Two host interface options: 16-bit parallel bus for speed, or 4-wire SPI for smaller footprint and interconnect wiring reduction.
- 64K bytes internal static RAM.
- Autonomous terminal operation requires minimal host intervention.
- Shared 1553 bus interface reduces circuit complexity and circuit board area.
- Fully programmable Bus Controller with 28 op code instruction set.
- Bus Monitor can operate in dual-stack mode, recording commands and data separately, with 16-bit or 48-bit time tagging.
- Bus Monitor can record commands and data in single-stack mode, using IRIG-106 Chapter 10 “packet body” format.
- Single-stack Bus Monitor and can optionally generate complete IRIG-106 data packets, including full packet headers and trailers.
- Independent 16-bit time tag counters and clock sources for all terminals. The Bus Controller and Monitor also have 32- and 48-bit time count options, respectively.
- 64-Word Interrupt Log Buffer queues the most recent 32 interrupts. Hardware-assisted interrupt decoding quickly identifies interrupt sources.
- RAM Error Detection/Correction option
- Built-in self-test for protocol logic, digital signal paths and internal RAM.
- Optional self-initialization at reset uses external serial EEPROM
- ±8kV ESD Protection (HBM, all pins).
- Two temperature ranges: -40°C to +85°C, or -55°C to +125°C with optional burn-in.
- RoHS compliant lead-free option.
Applications
- MIL-STD-1553 Terminals
- Flight Control and Monitoring
- ECCM Interfaces
- Stores Management
- Sensor Interfaces
- Test Equipment
- Instrumentation