The HI-6110 is a CMOS integrated circuit designed to implement the MIL-STD-1553 protocol between a host processor and a dual redundant MIL-STD-1553 data bus. The single chip architecture contains all the necessary logic and memory to process and store the data and command words for one complete MIL-STD-1553 message. In addition, the chip also includes the analog transceivers.

The HI-6110 may be configured as a Bus Controller (BC), a Remote Terminal (RT), an addresssed Monitor Terminal (MT) or an unaddressed MT. Registers are provided to store both incoming and outgoing command words. Incoming and outgoing data word storage is provided by 32-word FIFOs.

The HI-6110 is available in a small, 64-pin chip-scale package (LPCC) or a 52-pin plastic quad flat pack (PQFP).

• Monolithic CMOS Technology
• Exceptional Low Power
• On-chip Message Buffering
• 3.3V Single Supply Operation
• Compliant to MIL-STD-1553 Notice 2 and MIL-STD-1760 Stores Management
• Selectable Master Clock Frequency
• On-chip Dual Transceivers
• Bus Controller / Remote Terminal / Bus Monitor Mode Selection
• Smallest Footprint Available in 64-Pin 9mm x 9mm Plastic Chip-scale Package
• Also Available in a 52-pin Plastic QFP Option
• Industrial & Extended Temperature Ranges Available

• MIL-STD-1553 Terminals
• Flight Control and Monitoring
• ECCM Interfaces
• Stores Management
• Sensor Interfaces
• Test Equipment
• Instrumentation