Protocol IP Core

The Holt MIL-STD-1553/1760 IP solution is based on Holt’s HI-6130/31 and MAMBATM families and provides a complete single- or multi-function protocol interface between a host processor and MIL-STD-1553B bus. Any combination of BC, RT or MT functions can be operated concurrently. The enabled terminals communicate with the MIL-STD-1553 buses through a shared dual bus transceiver and external transformer, also available from Holt.


All RT devices are MIL-STD-1760 compliant, responding to valid messages with status word Busy Bit set within 150ms following power-on.


The Holt Multi-Core IP product includes a Verilog IP core, test bench, and supporting documentation, allowing designers to instantiate the core in a variety of FPGA implementations.




  • Fully software compatible with Holt’s existing hardware solutions: MAMBATM or HI-6130/31 families

  • Two product variants: BC/RT/MT or RT/MT

  • IP is based on fully validated IC solution

  • Available DO-254 Certification Package supporting Design Assurance Level A

  • Concurrent multi-terminal operation

  • Synchronous AXI Host Interface 

  • Built-in self-test feature

  • Fully programmable Bus Controller with 28 op code instruction set

  • Independent time-tag counters for all terminals with 32-bit option for Bus Controller and 48-bit option for Monitor Terminal

  • Simple Monitor Terminal (SMT) Mode records commands and data separately, with 16-bit or 48-bit time tag

  • 32-deep Interrupt buffer

  • MIL-STD-1760 Boot mode to initialize RT with Busy Bit set without host intervention